SIMMs and SIPPs
Through the 1970s, RAMs were shipped in tubes, and the board makers soldered them into boards or plugged them into sockets on boards. This became a problem when end-users started installing their own RAMs, because the leads ("pins") were too delicate. Also, the individual dual in-line package (DIP) sockets took up too much board area.

In the early 1980s, DRAM manufacturers began offering DRAMs on tiny circuit boards which snap into special sockets, and by the late '80s these "single in-line memory modules" (SIMMs) had become the most popular DRAM packaging. Board vendors who didn't trust the new SIMM sockets used modules with pins: single inline pinned packages (SIPPs), which plug into sockets with more traditional pin receptacles.

PC-compatibles store each byte in main memory with an associated check bit, or "parity bit." That's why you add memory in multiples of nine bits. The most common SIMMs present nine bits of data at each cycle (we say they're "nine bits wide") and have thirty contact pads, or "leads." (The leads are commonly called "pins" in the trade, although "pads" is a more appropriate term. SIMMs don't *have* pins!)

At the high end of the PC market, "36 bit wide" SIMMs with 72 pads are gaining popularity. Because of their wide data path, 36-bit SIMMs give the motherboard designer more configuration options (you can upgrade in smaller chunks) and allow bandwidth-enhancing tricks (i.e. interleaving) which were once reserved for larger machines. Another advantage of 72-lead SIMMs is that four of the leads are used to tell the motherboard how fast the RAMs are, so it can configure itself automatically.

"3-chip" and "9-chip" SIMMs
In 1988 and '89, when 1 megabit (1Mb) DRAMs were new, manufacturers had to pack nine RAMs onto a 1 megabyte (1MB) SIMM. Now (1993) 4Mb DRAMs are the most cost-effective size. So a 1MB SIMM can be built with two 4Mb DRAMs (configured 1M x4) plus a 1Mb (x1) for the check-bit.

VRAMs
In graphics-capable video boards, the displayed image is almost always stored in DRAMs. Access to this data must be shared between the hardware which continuously copies it to the display device (this process is called "display refresh" or "video refresh") and the CPU. Most boards do it by time-sharing ordinary, single-port DRAMs. But the faster, more expensive boards use specialized DRAMs which are equipped with a second data port whose function is tailored to the display refresh operation. These "Video DRAMs" (VRAMs) have a few extra pins and command a price premium. They nearly double the bandwidth available to the CPU or graphics engine.

Speed
DRAMs are characterized by the time it takes to read a word, measured from the row address becoming valid to the data coming out. This parameter is called Row Access Time, or tRAC. There are many other timing parameters to a DRAM, but they scale with tRAC remarkably well. tRAC is measured in nanoseconds (ns). A nanosecond is one billionth (10&sup9;) of a second.

It's so difficult to control the semiconductor fabrication processes that the parts don't all come out the same. Instead, their performance varies widely, depending on many factors. A RAM design that would yield 50ns tRAC parts if the fab were always tuned perfectly, instead yields a distribution of parts from 80ns to 50ns. When the plant is new, it may turn out mostly nominal 70 ns parts, which may actually deliver tRAC between 60.1ns and 70.0ns, at 70 or 85 degrees Celcius and 4.5 volts power supply. As it gets tuned up, it may turn out mostly 60ns parts and a few 50s and 70s. When it wears out it may get less accurate and start yielding more 70s again.

RAM vendors have to test each part off the line to see how fast it is.
An accurate, at-speed DRAM tester can cost several million dollars, and testing can be a quarter of the cost of the parts. The finished parts are not marked until they are tested and their speed is known.